1. Field of Invention
The present invention relates to a CRC encoding circuit for generating CRC bits from parallel data which is inputted as variable-length data, and to a CRC encoding method therefor. Further, the present invention relates to a data sending device and a data receiving device for detecting an error of data in the data communication by using the CRC encoding circuit.
2. Description of Related Art
According to an earlier development, a CRC (Cyclic Redundancy Check) which has high ability to detect an error in a digital communication, is used. The CRC means an error detection method for detecting an error of data by making a comparison between the CRC bits generated in a sender and the CRC bits generated in a receiver.
Recently, for example, like POS (PPP Over SONET/SDH), the high-speed variable-length data communication which performs communication from end to end by framing a low-speed variable-length data frame (PPP frame) over a high-speed variable-length data frame (SONET/SDH frame), is utilized widely. A CRC encoding circuit which generates CRC bits in accordance with the inputted n-byte(s) parallel data, has been introduced as means for detecting an error of data in such high-speed variable-length data communication.
Hereinafter, a former CRC encoder will be explained with reference to the drawings. FIG. 3 shows circuit composition of a CRC encoding circuit 21. As shown in FIG. 3, a CRC encoding circuit 21 mainly comprises a 16-bytes parallel CRC encoder 22, each n-byte(s) parallel CRC encoder 23 to 37 (n=1 to 15), and a selector (SEL) 38.
In the 16-bytes parallel data outputted from an external circuit, the parallel data other than the remainder portion data of the last column is encoded by the 16-bytes parallel CRC encoder 22. As a result, CRC bits are outputted as an encoded interim result. On the other hand, the remainder portion data of the last column is encoded by any one of the n-byte(s) parallel CRC encoders corresponding to the number of the byte(s) of the inputted remainder portion data, in accordance with the encoded interim result, and then is outputted to the SEL 38. The SEL 38 selects the desired CRC bits from the inputted plurality of CRC bits, and outputs the desired CRC bits as a final encoded result.
FIG. 4 is the view showing circuit composition of a former CRC encoding circuit 41. As shown in FIG. 4, the CRC encoding circuit 41 comprises a 16-bytes parallel CRC encoder 42, a byte serializer 43, a 1-byte serial CRC encoder 44, and a selector (SEL) 45.
In the 16-bytes parallel data outputted from an external circuit, the parallel data other than the remainder portion data of the last column is encoded by the 16-bytes parallel CRC encoder 42. As a result, CRC bits are outputted as an encoded interim result. On the other hand, the remainder portion data of the last column is converted to bytes serial data by the byte serializer 43. The converted data is encoded by the 1-byte serial CRC encoder 44 in accordance with the CRC bits, and is outputted to the SEL 45. Then, the SEL 45 selects the desired CRC bits from the inputted plurality of CRC bits, and outputs the desired CRC bits as a final encoded result.
Although the above-mentioned CRC encoding circuits 21 and 41 were useful as a remedy for processing less than 16 bytes of data, there were the following problems. Firstly, in the case that, for example, variable-length data is 16-bytes data, a total of 16 n-byte(s) parallel CRC encoders including the CRC encoder(s) which is not actually used, are required in the CRC encoding circuit 21. Thus, a total of 2n−1 byte(s) parallel CRC encoders are required as the number of bytes of the inputted 2n-byte(s) parallel data increases. Therefore, the manufacturing costs of the CRC encoding circuit increases with the circuit scale of the CRC encoding circuit.
Further, in the case of the CRC encoding circuit 41, although the generation of CRC bits can be realized with one byte parallel CRC encoder, the 1-byte serial CRC encoder is to be used 2n−1 times at the maximum when byte(s) parallel data is converted to byte(s) serial data. Thus, in the case that the n of the inputted 2n-bytes parallel data is 2 or more, variable-length data cannot be processed in sequential order.